This invention relates generally to computer memory, and more particularly to providing a non-power-of-two burst length in a memory system.
Contemporary high performance computing memory systems utilize error-detecting codes, such as parity bits or cyclic redundancy checks to detect occasional random bit errors. Other memory systems incorporate error correcting codes (ECC) to both detect and correct bit errors. As data rates increase in memory systems, error codes need to be transmitted along with data to ensure data integrity and high reliability. However, this increases the total number of bits transferred for each memory access, and thus, typically requires additional I/O pins or lanes and corresponding module/board signal traces and connector pins. Additional I/O pins increase overall memory system cost and may also result in additional failure modes. Therefore, it would be beneficial to send error-detecting codes bits without increasing the number of I/O pins.
Typical dynamic random access memory (DRAM) utilizes bursting in power-of-two lengths to improve data bandwidth. For example, double data rate one (DDR1) synchronous DRAM (SDRAM) may have a burst length of 2, DDR2 SDRAM may have a burst length of 4, and DDR3 SDRAM may have a burst length of 8, where each burst accesses data at locations relative to a specified memory address. It would be advantageous to develop an approach to modify memory system bursting to accommodate both data and error-detecting codes on the same data lines without reducing data bandwidth. Accordingly, there is a need in the art for providing a non-power-of-two burst length in a memory system.